DRAGSTER
DRAGSTER
Revision History:
Version
Date
3.2.2
09/09/15
Updated Document
Fátima Baptista
3.2.3
04/05/16
Update LCC Drawings
José Félix
3.2.4
13/05/16
Updated pinout
Fátima Baptista
3.2.5
29/06/16
Updated table 6
Fátima Baptista
3.2.6
01/08/16
Updated Spectral Response graph
José Félix
3.2.7
12/08/16
Updated package information
Fátima Baptista
3.2.8
06/06/17
Updated section 12
Fátima Baptista
Date: 06/06/17
Modifications
Version 3.2.8
Author
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Table of Contents
1 Introduction......................................................................................................................................................................8
2 Disclaimer.......................................................................................................................................................................10
3 General Statements and Conventions.............................................................................................................................11
3.1 Tolerances.................................................................................................................................................................11
3.2 Power supply.............................................................................................................................................................11
3.3 Clock specification...................................................................................................................................................11
3.4 Digital numbers.........................................................................................................................................................11
3.5 Metric units...............................................................................................................................................................11
4 Block Diagram................................................................................................................................................................12
5 External Components......................................................................................................................................................14
6 Electrical Description.....................................................................................................................................................18
6.1 Absolute Maximum Ratings.....................................................................................................................................18
6.2 Electrical overstress immunity..................................................................................................................................19
6.3 Latch-up immunity....................................................................................................................................................19
6.4 “Power ON” Sequence..............................................................................................................................................19
6.5 Operating Conditions................................................................................................................................................20
6.6 Electrical characteristics...........................................................................................................................................21
6.7 Optical characteristics DR-2k-7, DR-4k-7, DR-6k-7, DR-8k-7...............................................................................23
6.8 Optical characteristics DR-2x2k-7, DR-2x4k-7, DR-2x8k-7...................................................................................25
6.9 Optical characteristics DR-4k-3.5, DR-8k-3.5, DR-16k-3.5....................................................................................27
6.10 Dragster Relative Spectral Response......................................................................................................................29
6.10.1 Filter transmission for RGB Bayer pattern sensor versions............................................................................30
6.10.2 Color filter arrangement for RGB Dragster versions......................................................................................30
6.11 Placement of pixels DR-Xk-7.................................................................................................................................31
6.11.1 Test & special pixels DR-Xk-7 ......................................................................................................................31
6.12 Placement of pixels DR-Xk-3.5..............................................................................................................................32
6.12.1 Test & special pixels DR-Xk-3.5....................................................................................................................32
7 Functional Description....................................................................................................................................................33
7.1 General sensor description........................................................................................................................................33
7.1.1 Functional description Dragster Pixel..............................................................................................................35
7.1.1.1 Anti Blooming circuitry .......................................................................................................................36
7.1.1.2 Anti corona circuitry.............................................................................................................................37
7.1.1.3 Analogue Gain......................................................................................................................................37
7.1.1.4 CDS reference generation.....................................................................................................................37
7.1.1.5 Pixel Level ADC...................................................................................................................................38
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7.1.1.6 Digital Readout concept.......................................................................................................................42
7.2 Configuration Bit Overview......................................................................................................................................43
7.3 Register definition.....................................................................................................................................................45
7.3.1 CONTROL register 1.......................................................................................................................................45
7.3.2 CONTROL register 2.......................................................................................................................................46
7.3.3 Inversed ADC Gain Register............................................................................................................................47
7.3.4 Offset register...................................................................................................................................................48
7.3.5 CONTROL register 3.......................................................................................................................................48
7.3.6 Threshold register 1..........................................................................................................................................49
7.3.7 Threshold register 2..........................................................................................................................................50
7.3.8 Threshold register 3..........................................................................................................................................50
7.3.9 End of Range register.......................................................................................................................................50
7.3.10 Test Multiplexer register................................................................................................................................51
7.4 Serial 4 wire configuration interface.........................................................................................................................53
7.4.1 Writing Operation.............................................................................................................................................53
7.4.2 Reading Operation............................................................................................................................................54
7.5 Timing diagrams ......................................................................................................................................................55
8 Pins and functionality.....................................................................................................................................................58
9 Tap organization ............................................................................................................................................................59
9.1.1 Tap organization DR-2k-7, DR-4k-7, DR-8k-7..............................................................................................59
9.1.2 Tap organization DR-6k-7................................................................................................................................60
9.1.3 Tap organization DR-4k-3.5, DR-8k-3.5, DR-16k-3.5....................................................................................61
9.1.4 Tap organization DR-2x2k-7, DR-2x4k-7, DR-2x8k-7....................................................................................62
9.1.5 Tap organization DR-2x2k-7-RGB, DR-2x4k-7-RGB, DR-2x8k-7-RGB.......................................................63
10 Packages overview........................................................................................................................................................64
11 Mechanical Drawings...................................................................................................................................................67
11.1 LCC Package drawings DR2k-7.............................................................................................................................67
11.2 LCC package drawings DR2x2k-7, DR4k-3.5.......................................................................................................68
11.3 Invar package drawing DR4k-7 .............................................................................................................................69
11.4 Incar package drawing DR-2x4k-7, DR8k-3.5.......................................................................................................70
11.5 Invar package drawing DR2k-7, DR2x2k-7, DR4k-3.5.......................................................................................71
11.6 Invar package drawing DR6k-7..............................................................................................................................72
11.7 Invar package drawing DR8k-7..............................................................................................................................73
11.8 Invar package drawing DR-2x8k-7, DR-16k-3.5....................................................................................................74
12 Connectors pin outlined................................................................................................................................................75
12.1 Pinout DR2k-7-LCC, DR2x2k-7-LCC, DR4k-3.5-LCC........................................................................................75
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12.2 Connectors for different versions of Invar headboard packages.............................................................................78
12.2.1 Connector number identification and pin numbers.........................................................................................79
.........................................................................................................................................................................................79
12.3 Connector signal assignment for Invar head board DR-2x2k-7-Invar, DR-4k-3.5-Invar, DR-2k-7-Invar.............80
12.3.1 Connector 1 ...................................................................................................................................................80
12.3.2 Connector 2 ...................................................................................................................................................83
12.4 Connector signal assignment for Invar head board variations DR-4k-7, DR-8k-7, DR-8k-3.5, DR-16k-3.5, DR2x4k-7, DR-2x8k-7..........................................................................................................................................................86
12.4.1 Connector 1 ...................................................................................................................................................86
12.4.2 Connector 2 ...................................................................................................................................................89
12.4.3 Connector 3 ..................................................................................................................................................92
12.4.4 Connector 4 ...................................................................................................................................................95
12.5 Connector signal assignment for Invar head board DR-6K-7.................................................................................98
Index of Tables
Table 1: Recommended values for capacitors and inductances..........................................................................................15
Table 2: Optional external components..............................................................................................................................16
Table 3: Absolute maximum ratings ..................................................................................................................................18
Table 4: Operating conditions............................................................................................................................................20
Table 5: Electrical characteristics.......................................................................................................................................21
Table 6: Power consumption for Dragster Invar package .................................................................................................22
Table 7: Power consumption for Dragster LCC package...................................................................................................22
Table 8: Optical characteristics for DR-2k-7, DR-4k-7, DR-6k-7, DR-8k-7 ...................................................................23
Table 9: Optical Characteristics for DR-2x2k-7, DR-2x4k-7, DR2x8k-7..........................................................................26
Table 10: Optical characteristics DR-4k-3.5, DR-8k-3.5, DR-16k-3.5..............................................................................27
Table 11: Test multiplexer channels...................................................................................................................................52
Table 12: Pins and functionality.........................................................................................................................................58
Table 13: Package overview...............................................................................................................................................66
Table 14: Connectors for different chip versions...............................................................................................................78
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Index of Figures
Fig 1: Block diagram of a Dragster Element......................................................................................................................13
Fig 2: Recommended power supply strategy for the sensor head board. *The component DAC1 is optional...................14
Fig 3: External components for the option to control the ADC offset by an external DAC for the case of a sensor with 4
segments..............................................................................................................................................................................16
Fig 4: Equivalent load scheme for use of external DAC....................................................................................................17
Fig 5: Dragster Relative Spectral Response measured according EMVA1288..................................................................29
Fig 6: Spectral transmission of colour filters......................................................................................................................30
Fig 7: Color filter arrangement on Dragster dual line sensors............................................................................................30
Fig 8: Placement of pixels sensors with 7um pixel pitch....................................................................................................31
Fig 9: Placement of pixels sensor variations with 3.5μm pixel pitch.................................................................................32
Fig 10: Interconnection of ADC reference voltages in case of 7μm pixel pitch sensors with multiple segments..............33
Fig 11: Interconnection of ADC reference voltages in case of 3.5μm pixel pitch sensors with multiple segments..........34
Fig 12: Overview of pipelined integration ADC and readout sequence.............................................................................35
Fig 13: Overview of the functional blocks for the analogue part of the pixel....................................................................36
Fig 14: Functional block diagram of the pixel level ADC..................................................................................................38
Fig 15: ADC transfer function in linear mode and registers defining the ADC parameters...............................................39
Fig 16: ADC transfer function in companding mode..........................................................................................................40
Fig 17: Adaptation of the ADC conversion step in companding ADC mode.....................................................................41
Fig 18: Writing operation...................................................................................................................................................53
Fig 19: Reading operation..................................................................................................................................................54
Fig 20: Timing diagram......................................................................................................................................................55
Fig 21: Timing diagram......................................................................................................................................................56
Fig 22: Detail end of integration start ADC and readout....................................................................................................57
Fig 23: Tap organization DR-2k-7, DR-4k-7, DR-8k-7.....................................................................................................59
Fig 24: Tap organization DR-6k-7.....................................................................................................................................60
Fig 25: Tap organization DR-4k-3.5, DR-8k-3.5, DR-16k-3.5..........................................................................................61
Fig 26: Tap organization DR-2x2k-7, DR-2x4k-7, DR-2x8k-7.........................................................................................62
Fig 27: Tag organization DR-2x2k-7-RGB, DR-2x4k-7-RGB, DR-2x8k-7-RGB.............................................................63
Fig 28: Four Views of LCC Package Drawings for DR2k-7 .............................................................................................67
Fig 29: Four Views of LCC Package Drawings for DR2x2k-7 B&W and RGB, DR4k-3.5..............................................68
Fig 30: Top view DR-B&W-4k-7-Invar. If not otherwise noted all tolerances are +/- 0.1mm..........................................69
Fig 31: DR-B&W-4k-7-Invar. Tolerance +/- 0.1mm.........................................................................................................69
Fig 32: Top view DR-B&W-2x4k-7-Invar and DR-B&W-8K-3.5-Invar. If not otherwise noted all tolerances are +/0.1mm.................................................................................................................................................................................70
Fig 33: DR-B&W-2x4k-7-Invar, DR-B&W-8K-3.5-Invar. Tolerance +/- 0.1mm.............................................................70
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Fig 34: Top view DR-B&W-2k-7-Invar, DR-B&W-2x2k-7-Invar, DR-B&W-4k-3.5-Invar. If not otherwise noted all
tolerances are +/- 0.1mm....................................................................................................................................................71
Fig 35: DR-B&W-2k-7-Invar, DR-B&W-2x2k-7-Invar, DR-B&W-4k-3.5-Invar.. Tolerance +/- 0.1mm......................71
Fig 36: Top view DR-B&W-6k-7-Invar. If not otherwise noted all tolerances are +/- 0.1mm..........................................72
Fig 37: DR-B&W-6k-7-Invar. Tolerance +/- 0.1mm.........................................................................................................72
Fig 38: Top view DR-B&W-8k-7-Invar. If not otherwise noted all tolerances are +/- 0.1mm..........................................73
Fig 39: DR-B&W-8k-7-Invar. Tolerance +/- 0.1mm.........................................................................................................73
Fig 40: Top view DR-B&W-2x8k-7-Invar and DR-B&W-16k-3.5-Invar. If not otherwise noted all tolerances are +/0.1mm.................................................................................................................................................................................74
Fig 41: DR-B&W-2x8k-7-Invar, DR-B&W-16k-3.5-Invar. Tolerance +/- 0.1mm............................................................74
Fig 42: Identification of connector number and pin numbers, DR-16K-3.5 back view ....................................................79
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DRAGSTER
1 Introduction
DRAGSTER is a platform of a digital line-scan sensors. The sensor family is made using three
types of basic elements: a single line element with 2048 pixel resolution and 7μm pixel size and
pitch, a dual line element with 2048 pixel resolution and 7μm pixel size and pitch and a 4096
pixels element with 3.5μm pixel size and pitch. Any of the following types can be made, where
“1x” means single line and “2x” means dual line:
Line
Resolution
2K
4K
1x
6K
8K
16K
2K
2x
4K
8K
The chip versions with dual line are optionally available with Bayer Pattern RGB filters placed on
the sensors.
For all variations the basic readout and control electronics are identical. Other different variations of
pixel aspect ratios can be implemented, please contact AWAIBA if you require customized
resolution sensors based on Dragster architecture.
The current specification covers the following device variations:
Part Number
Number of pixels
Pixel size
Package Type
DR-B&W-2K-7-LCC
1x2048
7μm x 7μm
LCC
DR-B&W-2K-7-Invar
1x2048
7μm x 7μm
Invar module
DR-B&W-4K-3.5-LCC
1x4096
3.5μm x 3.5μm
LCC
DR-B&W-4K-3.5-Invar
1x4096
3.5μm x 3.5μm
Invar module
DR-B&W-4K-7-Invar
1x4096
7μm x 7μm
Invar module
DR-B&W-6K-7-Invar
1x6175
7μm x 7μm
Invar module
DR-B&W-8K-3.5-Invar
1x8192
3.5μm x 3.5μm
Invar module
DR-B&W-8K-7-Invar
1x8192
7μm x 7μm
Invar module
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DR-B&W-16K-3.5-Invar
DR-B&W-2x2K-7-LCC
DR-RGB-2x2K-7-LCC
DR-B&W-2x2K-7-Invar
DR-RGB-2x2K-7-Invar
DR-B&W-2x4K-7-Invar
DR-RGB-2x4K-7-Invar
1x16384
3.5μm x 3.5μm
Invar module
2x2048
7μm x 7μm
LCC
2x2048
7μm x 7μm
Invar module
2x4096
7μm x 7μm
Invar module
7μm x 7μm
Invar module
DR-B&W-2x8K-7-Invar**
2x8192
DR-RGB-2x8K-7-Invar**
** sales restrictions may apply to some markets
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2 Disclaimer
The Integrated Circuit (IC) has been or will be designed and developed so as to conform in all
material respects to the preceding introduced specification based on the performance indication and
guideline from the silicon manufacturer regarding the target CMOS technology. Any change to the
specification shall be mutually consulted and determined with the prior written consent of the
parties. Any changes to the specifications required by the Customer shall be mutually agreed upon
and laid down in writing as a supplement to or correction of the specifications.
AWAIBA does not warrant and Customer therefore expressly waives the existence of any
parameters or features of the IC, which are not explicitly mentioned in the specification. It is the
customer’s responsibility and obligation to check compliance of the IC to the requirements of the
application. The IC will not be designed for use as critical 1 component in medical, military or live
sustaining 2 applications. Any use of the IC without prior written consent of AWAIBA in such
applications is prohibited.
The above mentioned warranty is the only warranty given by AWAIBA. AWAIBA expressly
disclaims all other warranties, whether expressed, implied, or statutory, including, without
limitation, any implied or statutory warranties of merchantability, fitness for a particular purpose,
and non-infringement, and any warranty that may arise by reason of usage of trade, custom or course
of dealing, and customer hereby expressly waives any such warranties.
1) A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
2) Life support devices, systems or applications are devices, systems or applications which, (a) are intended for surgical implant into the body, or (b)
support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected
to result in a significant injury to the user.
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DRAGSTER
3 General Statements and Conventions
Info only
Text in this document between “{ info only:” and “end info}” or “{“ and “}” is for information
only. Parameters and information given in this section contain background information .
Performance and parameters given in these sections can not be guaranteed. No implicit nor explicit
specification can be derived from these sections.
3.1 Tolerances
For all parameters, nominal value, upper, and lower bound of guaranteed specification are indicated.
Parameters indicated without tolerances are for info only and can not be guaranteed.
3.2 Power supply
The lowest supply voltage in the chip is referred to as VSS. VSSxx indicates the lowest power
supply voltage of a sub block xx of the circuit. All VSS power supply’s have the same potential at
all pins at any time. 0V is defined as being the voltage applied to the VSS pins.
The highest supply voltage of a sub block xx of the circuit is referred to as VDDxx. All pins
carrying identical VDDxx power supply net labels have the same potential at any time, neglecting
parasitic effects.
All voltage specifications are referred to VSS unless otherwise specified. All positive currents flow
into a pin. The sinking of current means that current is flowing into a pin. The sourcing of current
means that current is flowing out of a pin.
3.3 Clock specification
All timing information treated by a digital control part refers to the master clock frequency which is
supplied on pin Main clk, unless otherwise specified.
3.4 Digital numbers
When ever referred to the output signal this is indicated in DN (Digital Numbers) equalling 1 unit
(1LSB) of the on chip ADC. This quantity is sometimes also referred to as "grey levels".
3.5 Metric units
Unless otherwise indicated all measurements and units follow metric units. Mechanical dimensions
are by default given in mm.
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4 Block Diagram
The sensor features a low noise pixel with true CDS and global shutter for interleaved readout and
integration operation. Each pixel has an on pixel ADC and 13bit readout register. AD conversion is
made to 12.2 bits and for output clamped to 12bit to guarantee full 4096 DN signal swing. The
ADC gain can be programmed in a range of -6dB till + 20 dB by means of an 8bit DAC controlled
over the serial configuration interface.
The readout is made by 2 12bit wide digital taps organized in odd / even order for each 2k segment.
(full 13 bit readout is possible for special purposes). For each line segment, all 2k pixels have to be
read out.
For sensor versions with 3.5μm pixel pitch, two 2k segment readout circuits are placed on each side
of the pixel line, to lead to a basic segment of 4k pixels, even pixels read out over the bottom
readout, odd pixels read out over the top readout.
Start of integration, end of integration and optional start of readout are started upon individual
external trigger events. To enhance dynamic range multiple non destructive readouts are possible.
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3 .3 V
P o w e r s u p p ly p e r b lo c k a n d b lo c k d ia g r a m
V D D _ b u lk
fo r 1 2 k s e g m e n t
3 .3 V
V S S _ b u lk
VD DA
3 .3 V
VSSA
VD DD
2 .4 -3 .3 V
VSSD
V D D _ IO
3 .3 V
V S S _ IO
VD D_ESD
VSS_ESD
c o m p le t e 2 k s e g m e n ts a r e r e p e a te d f o r 4 k o r 8 k s e n s o r s
RESET_C VC
P ix e l
P ix e l
B ia s & R e fe r e n c e
g e n e r a tio n
P ix e l
R ST_CD S
C D S S ta g e
C D S S ta g e
C D S S ta g e
SC LK
x4
x4
x4
SPI
n_CS
SAM PLE
S&H
S&H
S&H
M O SI
M IS O
A
A
A
D
D
D
13b
13b
13b
A D C C o n tro l
EN D_AD C
1 3 b it s h a d o w r e g is te r
N_RESET
M A IN _ C L K
g lo a s b a l
lo g ic
re s e t n e t
g lo b a l c lk
net
13b
1 3 b it s h a d o w r e g is te r
1 3 b it s h a d o w r e g is te r
13b
13b
26b
1 3 b it r e a d o u t r e g s ite r
1 3 b it re a d o u t r e g s ite r
1 3 b it r e a d o u t r e g s ite r
D O U T [0 :2 5 ]
O f fs e t S u b tr a c tio n ; 1 2 b it s a t u r a tio n
26b
26b
13b
13b
26b
1 3 b it o f fs e t r e g s it e r
B it _ [0 0 . .1 2 ]_ T a p A
13b
1 3 b it o ff s e t r e g s it e r
B it _ [0 0 . .1 2 ]_ T a p B
1 3 b it o f fs e t r e g s it e r
LVAL
LO AD _PU LSE
R e a d o u t c o n tro l
Fig 1: Block diagram of a Dragster Element
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5 External Components
L1
VDDA
C2
Board Contact for VDDA
1X
1X
C3
C4
GND
Board Contact for GND
L1
VDD_bulk
1X
C2
C3
GND
VDDESD
GND
L1
1X
1X
C3
C4
L1
VDDD
1X
VDDIO
Board Contact for VDDD
1X
C3
C4
1X
C2
GND
DAC1*
TEST_MUX_xx
GND
C3
C2
Fig 2: Recommended power supply strategy for the sensor head board. *The component DAC1 is
optional
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Component
Description
Nominal value
Tolerance
Voltage range
C2
Power decoupling capacitor,
close to each VDDx
connector pin
10nF
+/- 25%
>3.6V
low ESR Ceramic
C3
Power decoupling capacitor,
placed one time per power
supply. Tantal type.
10uF
+/- 25%
>3.6V
C4
Power decoupling capacitor,
placed one time per power
supply. Tantal type.
100uF
+/- 25%
>3.6V
L1
Power decoupling inductance
10nH
+/- 25%
dimension
according power
consumption of
respective
sensor variation
C5
Additional decoupling
capacitor on the outputs of
TEST_MUX *
10nF
+/- 25%
>3.6V
Table 1: Recommended values for capacitors and inductances
* optional additional components 1) If the “TEST_MUX_XX_#” signals are accessible an
additional capacitance should be placed in this signal and then by writing Register 0x0A with
the value 0x0F the line by line offset noise is reduced significantly.
{ info only:
The external circuit schematic to be used for this solution is shown in Figure 3, where an
external DAC is used to set the ADC offset (black reference) in more fine steps and possibly
with better temperature stability, though for most applications the external DAC is not
necessary. If the “TEST_MUX_XX_#” signals are accessible, an external DAC can be used to
directly set the ADC offset. To achieve that the “TEST_MUX_XX_#” outputs should be
connected and 0x0F should be written to register 0x0A in all segments. Also, make sure the
DAC output impedance is higher than 200KOhm. Such DAC may permit to provide more fine
tuning to the pixel black level. On chip there is an 8 bit resolution DAC for this purpose but
an external ADC can provide benefit if more fine adjustment steps are required. For sensors
with 3.5μm pixel or dual line sensors such DAC has to be provided for top and bottom side
separately, though is not mandatory.
Once the individual DAC offset's are equalized over the external connection, the black level
can be adjusted by writing the same value to the registers on each segment.
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In case of sensors with readout tap's on top and bottom side different values can be written on
top and bottom side SPI's in order to equalize the odd even pixels offset, respectively the line
offset.
DAC 1
Write 0x0F on Reg.
0x0A
in all segments
DAC 1
TEST_MUX_GH_2
TEST_MUX_EF_2
TEST_MUX_GH_1
TEST_MUX_CD_2
TEST_MUX_AB_2
DRAGSTER
SENSOR HEAD
BOARD
TEST_MUX_EF_1
TEST_MUX_CD_1
TEST_MUX_AB_1
C1
C1
Fig 3: External components for the option to control the ADC offset by an external DAC for the case
of a sensor with 4 segments.
Component
Description
Nominal value
DAC 1
Optional additional
DAC on outputs of
TEST_MUX
1V – 2.5V (or
wider)
Tolerance
Output resistance < 1k
Ohm
Voltage
range
>3.6V
Vnoise rms < 0.5mV
Table 2: Optional external components
In order to adjust the ADC black reference an external reference voltage is supplied via the
DAC where lowering the voltages shifts the output signal to higher digital values.
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Figure 4 illustrates the equivalent internal circuit when using an external DAC to set the black
level reference. The load circuit the DAC sees is in parallel for as many segments are
connected to the same DAC.
Dragster Sensor
VDDA
VDDA
Set by Reg 0x04
~20uA
Testmux
Channel 15
A
Vref black
Internal 1V - 2V
D
63k Ohm
VSSA
VSSA
VSSA
Fig 4: Equivalent load scheme for use of external DAC
: end info }
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6 Electrical Description
The sensor will comply to the specifications listed in this section within the operating ranges
listed in the respective section.
An applied signal must not have a deviation from the ideal signal, at the pin of the circuit,
such that the circuit or the parameter under test are affected significantly.
Proper decoupling of the circuit according to chapter 5 is required. The following section
defines the limits of functional operation and parametric characteristics of the circuit, and
reliability. Note that functionality of the circuit outside the operating range as specified in this
section is not guaranteed.
6.1 Absolute Maximum Ratings
Stresses above those listed in this clause may cause immediate and permanent device failure.
Operation outside the operating conditions for extended periods may affect device reliability.
It is not implied that more than one of these conditions can be violated simultaneously.
Total cumulative dwell time above the maximum operating rating for temperature must be
less than 100 hours.
Symbol
Description
Min
Max
Unit
VDD
Power supply voltage (digital)
-0.3
3.6
V
VIO
Voltage on any IO
-0.3
VDDIO +0.3 or
3.6
V
IIO
DC forward BIAS current, input or output
-24 (source) +24
(sink)
mA
Tj
Junction temperature
-55
125
C
Ta
Operating Temperature Range*
0
60
C
Table 3: Absolute maximum ratings
*The Operating Temperature Range is regarding the ambient temperature that is more suitable for a good
performance of the sensor. It is considered with no heat dissipation, since it's the environment temperature.
Date:
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DRAGSTER
6.2 Electrical overstress immunity
Electrostatic discharges on component level:
The device withstands 1k Volts Human Body Model ESD pulses when tested according to
MIL STD 883 method 3015.7
6.3 Latch-up immunity
Static latch-up protection level is 10mA at 25°C when tested according to EIA/JESD78.
6.4 “Power ON” Sequence
To avoid latch up problems that can create faulty operation points, the correct sequential
“Power On” sequence for all devices in INVAR headboard package is:
1) VDDESD
2) VDDA
3) VDD_BULK
4) VDDD
5) VDDIO
6) ramp up signals on any inputs
7) release N_RESET_XX
If the control over all supplies is not possible, at least care must be taken for the sensor
supplies to raise up in the following order:
1) VDDESD
2) VDD_BULK; VDDA; VDDD; VDDIO
3) ramp up signals on any inputs
4) release N_RESET_XX
For the LCC package versions, it is important that VDD ramps prior to any digital input
signal.
In any condition the two following situations are to be avoided:
Fault A: any VDDx is supplied before VDDESD or to a higher value than VDDESD
Fault B: digital inputs are supplied prior to supply of VDDESD
Date:
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DRAGSTER
6.5 Operating Conditions
Symbol
VDDD
VDDA
VDDESD
VDDIO
GND
Fclk
Duty clk
Duty clk
Jitter clk
Description
Power supply voltage
(digital)
Power supply voltage
(analogue)
Power supply voltage ESD
Power supply voltage IO
Ground supply
Input Clock Frequency
Input Clock Duty cycle up
to 50MHz
Input Clock Duty cycle up
to >50MHz
Vil
Vih
High level input voltage
Tj
VnrmsVDDD
VnppVDDD
VnrmsVDDA
VnppVDDA
VnrmsVDD/IO
VnppVDD/IO
Tsetup, data in
Thold, data in
Tsetup, MOSI
Thold, MOSI
Typical
Max
Unit
3.2
3.3
3.4
V
3.2
3.3
3.4
V
3.2
2.4*
3.3
3.3
0
3.4
3.4
85***
V
V
V
MHz
1**
45
55
70
%
55
57
65
%
=1us
SAMPLE (input)
RST_CDS (input)
7
conversion time (CT) + 5
end_adc (output)
RST_CVC (input)
1
4
>=1us
>=1us
>=1us
NOTE 1: rising of load = the later of ( rising edge end_adc; falling edge LVAL) + 4
NOTE 2: rising of LVAL = rising edge of load_pulse + 8
NOTE 3: falling of end_adc = falling edge of SAMPLE + 6
Conversion time:
if ADC_mode_bit =0)
CT = end_range*32
else (ADC_mode_bit = 1)
CT = [thr1+ (thr2-thr1)/2 + (thr3-thr2)/4 + (end_range -thr3)/8]*32
Fig 22: Detail end of integration start ADC and readout
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DRAGSTER
8 Pins and functionality
Pin Name
In-Out
Out_CVC_x
in/out
Out_CDS_x
in/out
SAMPLE
Dig in
Function
CVC output for pixel X, leave open or privide pull
up/down to fix read value.
CDS output for pixel X, leave open or privide pull
up/down to fix read value.
Sample signal
RST_CVC
RST_CDS
N_CS
SCLK
MOSI
MISO
VDDA
VDD_Bulk
VDDD
Dig in
Dig in
Dig in
Dig in
Dig in
Dig out
-
Reset signal for CVC
Reset signal for CDS
Negative Chip Select for serial interface
Serial clock for serial interface
Master out / Slave in line for serial interface interface
Master in / Slave out line for serial interface interface
Analog power supply
Bulk power supply
Digital power supply
VDDESD
-
VDDIO
VSSA
VSS_Bulk
VSSD
VSSESD/IO
LVAL
load_pulse
Dig out
Dig in
I/O power supply
Analog ground
Bulk ground
Digital ground
ESD protection and I/O ground
Line valid signal
Pulse to be shift on readout chain
Bit 0..12
Dig out
Bits from readout
end_adc
Dig out
İndication from counter beeing in reset
main_clk
Dig in
Main clock input
test_mux
NC
Vref
n_reset
NC
Dig in
VDD_05
NC
Vclamp
VDDA
Connect to VDDA
Pixel_clock
Dig out
Outuptu pixel clock (freqeuncy only differs from main
clock if clok diff is used)
ESD protection power supply
Leave open
Leave open
Global reset signal. Low active
Leave open
Table 12: Pins and functionality
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DRAGSTER
9 Tap organization
9.1.1 Tap organization DR-2k-7, DR-4k-7, DR-8k-7
A1
1
4K_7um
2K_7um
31
Black Pixels
Bottom, Connector 1
Readout Direction
B1
A2
B2
F1
Bottom, Connector 3
6173
E2
F2
Active Pixels
4127
4128
4129
4130
8K_7um
E1
2081
6175
6176
6179
8221
Fig 23: Tap organization DR-2k-7, DR-4k-7, DR-8k-7
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DRAGSTER
9.1.2 Tap organization DR-6k-7
B1
30
32
Top, Connector 2
Bottom, Connector 1
Readout Direction
A1
A2
B2
2081
E1
F1
6174
Fig 24: Tap organization DR-6k-7
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DRAGSTER
9.1.3 Tap organization DR-4k-3.5, DR-8k-3.5, DR-16k-3.5
Readout Direction
A1
B
1
C1
1
D1
63
Bottom, Connector 1
65
66
8K_3.5um
Top, Connector 2
4K_3.5um
61
...
A2
C2
D2
...
8252
8254
8255
E1 8256
8257
F1 8258
8259
16K_3.5um
B2
G1
H1
...
Top, Connector 4
Bottom, Connector 3
12349
12351
E2 12352
F2
12355
G2
H2
16445
16446
16447
Fig 25: Tap organization DR-4k-3.5, DR-8k-3.5, DR-16k-3.5
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DRAGSTER
9.1.4 Tap organization DR-2x2k-7, DR-2x4k-7, DR-2x8k-7
31
30
32
33
2078
2080
2081 2081
C2
D2
E1
F1
4127
4128 4128
4129 4129
4130
G1
H1
2x8K_7um
4126
Top, Connector 2
2079
D1
2x4K_7um
A2
B2
C1
0
1
2x2K_7um
Bottom, Connector 1
Readout Direction
A1
B1
E2
F2
6176
6177
6178 6178
6179 6179
Top, Connector 4
Bottom, Connector 3
6173 6173
6174
G2
H2
8221 8221
8222 8222
8223 8223
Fig 26: Tap organization DR-2x2k-7, DR-2x4k-7, DR-2x8k-7
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DRAGSTER
9.1.5 Tap organization DR-2x2k-7-RGB, DR-2x4k-7-RGB, DR-2x8k-7-RGB
30
4127
2x8K_7um_RGB
4128
4129
C2
D2
Top, Connector 2
32
33
2078
2079
2080
2081 2081
4126
E1
F1
D1
2x4K_7um_RGB
31
32
A2
B2
C1
0
1
2x2K_7um_RGB
Bottom, Connector 1
Readout Direction
A1
B1
G1
H1
4130
E2
F2
6178
6179
8221
8222
6176
6177
Top, Connector 4
Bottom, Connector 3
6173
6174
G2
H2
8223
Fig 27: Tag organization DR-2x2k-7-RGB, DR-2x4k-7-RGB, DR-2x8k-7-RGB
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DRAGSTER
10 Packages overview
DRAGSTER sensors are supplied with specific packages developed at Awaiba that are made
to bring serious advantages to camera developers. They include years of close development
with Awaiba's customers in the most demanding applications.
The available packages are organized in two main types: LCC and INVAR. The LCC is a no
lead package where the silicon's carrier is FR4 while the INVAR package uses a special nickel
iron alloy as heat dissipation and mechanical reference. While the LCC package is oriented for
size, resolution and cost conscious applications the INVAR type is focused on high
performance, where highest speed and high resolutions are the main advantages to the field
application. All package types take a cover glass over sensor's silicon to protect from external
dust particles. Optionally, the sensor can be delivered without cover glass and a globe top
protection of bond wires.
For the customer, one of the most obvious advantage of Dragster packages are the use of
commercially available connectors or low cost LCC connections. This makes each camera
development fast and easy and brings also other advantages: precise mechanical alignment to
the optics by taking INVAR as reference and it's CNC machined features, integrated heat
dissipation plate that minimizes sensor stress in Z-axis, maximization of sensor performance
in speed and noise and easily customizable package to suit any requirement. Furthermost the
LCC can also be mounted as a SMD part.
Other packages are possible, like bare die or CSP, so contact AWAIBA if you require a custom
package.
Date:
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DRAGSTER
Package
Sensors
Top View
Bottom View
DR-2K-7
LCC
DR-2x2K-7
DR-4K-3.5
Invar with 1 connector
DR-4K-7
DR-2K-7
DR-2x2K-7
DR-4K-3.5
Connector
Connector 22
Invar with 2 connectors
DR-2x4K-7
DR-8K-3.5
Connector 11
Connector
Connector 2
DR-6K-7
Connector 1
Invar with 2 connectors
in the bottom
Date:
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Version 3.2.8
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DRAGSTER
Invar with 4 connectors
DR-2x8K-7
DR-16K-3.5
Table 13: Package overview
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DRAGSTER
11 Mechanical Drawings
11.1 LCC Package drawings DR2k-7
Fig 28: Four Views of LCC Package Drawings for DR2k-7
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DRAGSTER
11.2 LCC package drawings DR2x2k-7, DR4k-3.5
Fig 29: Four Views of LCC Package Drawings for DR2x2k-7 B&W and RGB, DR4k-3.5
Date:
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DRAGSTER
11.3 Invar package drawing DR4k-7
Fig 30: Top view DR-B&W-4k-7-Invar. If not otherwise noted all tolerances are +/- 0.1mm
Fig 31: DR-B&W-4k-7-Invar. Tolerance +/- 0.1mm
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DRAGSTER
11.4 Incar package drawing DR-2x4k-7, DR8k-3.5
Fig 32: Top view DR-B&W-2x4k-7-Invar and DR-B&W-8K-3.5-Invar. If not otherwise noted all
tolerances are +/- 0.1mm
Fig 33: DR-B&W-2x4k-7-Invar, DR-B&W-8K-3.5-Invar. Tolerance +/- 0.1mm
Date:
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DRAGSTER
11.5 Invar package drawing DR2k-7, DR2x2k-7, DR4k-3.5
Fig 34: Top view DR-B&W-2k-7-Invar, DR-B&W-2x2k-7-Invar, DR-B&W-4k-3.5-Invar. If not
otherwise noted all tolerances are +/- 0.1mm
Fig 35: DR-B&W-2k-7-Invar, DR-B&W-2x2k-7-Invar, DR-B&W-4k-3.5-Invar.. Tolerance +/0.1mm
Date:
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DRAGSTER
11.6 Invar package drawing DR6k-7
Fig 36: Top view DR-B&W-6k-7-Invar. If not otherwise noted all tolerances are +/- 0.1mm
Fig 37: DR-B&W-6k-7-Invar. Tolerance +/- 0.1mm
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DRAGSTER
11.7 Invar package drawing DR8k-7
Fig 38: Top view DR-B&W-8k-7-Invar. If not otherwise noted all tolerances are +/- 0.1mm
Fig 39: DR-B&W-8k-7-Invar. Tolerance +/- 0.1mm
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DRAGSTER
11.8 Invar package drawing DR-2x8k-7, DR-16k-3.5
Fig 40: Top view DR-B&W-2x8k-7-Invar and DR-B&W-16k-3.5-Invar. If not otherwise noted all
tolerances are +/- 0.1mm
Fig 41: DR-B&W-2x8k-7-Invar, DR-B&W-16k-3.5-Invar. Tolerance +/- 0.1mm
Date:
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DRAGSTER
12 Connectors pin outlined
12.1 Pinout DR2k-7-LCC, DR2x2k-7-LCC, DR4k-3.5-LCC
Pin
Signal Name
DR-4k-3.5-LCC
DR-2x2k-7-LCC
Signal Name
DR-2k-7-LCC
Type
1
Tap A1 Bit 11
Tap A1 Bit 11
Digital Output
2
Tap A1 Bit 9
Tap A1 Bit 9
Digital Output
3
Tap A1 Bit 7
Tap A1 Bit 7
Digital Output
4
Tap A1 Bit 5
Tap A1 Bit 5
Digital Output
5
Tap A1 Bit 3
Tap A1 Bit 3
Digital Output
6
Tap A1 Bit 1
Tap A1 Bit 1
Digital Output
7
VSS
VSS
Ground
8
LVAL Tap A1/B1
LVAL Tap A1/B1
Digital Output
9
Tap A1 Bit 12
Tap A1 Bit 12
Digital Output
10
Tap A1 Bit 10
Tap A1 Bit 10
Digital Output
11
Tap A1 Bit 8
Tap A1 Bit 8
Digital Output
12
Tap A1 Bit 6
Tap A1 Bit 6
Digital Output
13
Tap A1 Bit 4
Tap A1 Bit 4
Digital Output
14
Tap A1 Bit 2
Tap A1 Bit 2
Digital Output
15
Tap A1 Bit 0
Tap A1 Bit 0
Digital Output
16
Pixel_CLK_Tap A1/B1
Pixel_CLK_Tap A1/B1
Digital Output
17
END_ADC_TAP A1/B1
END_ADC_TAP A1/B1
Digital Output
18
VSS
VSS
Ground
19
Tap B1 Bit 1
Tap B1 Bit 1
Digital Output
20
Tap B1 Bit 3
Tap B1 Bit 3
Digital Output
21
Tap B1 Bit 5
Tap B1 Bit 5
Digital Output
22
Tap B1 Bit 7
Tap B1 Bit 7
Digital Output
23
Tap B1 Bit 9
Tap B1 Bit 9
Digital Output
24
Tap B1 Bit 11
Tap B1 Bit 11
Digital Output
25
Tap B1 Bit 0
Tap B1 Bit 0
Digital Output
26
Tap B1 Bit 2
Tap B1 Bit 2
Digital Output
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DRAGSTER
Pin
Signal Name
DR-4k-3.5-LCC
DR-2x2k-7-LCC
Signal Name
DR-2k-7-LCC
Type
27
Tap B1 Bit 4
Tap B1 Bit 4
Digital Output
28
VSS
VSS
Ground
29
Tap B1 Bit 6
Tap B1 Bit 6
Digital Output
30
Tap B1 Bit 8
Tap B1 Bit 8
Digital Output
31
Tap B1 Bit 10
Tap B1 Bit 10
Digital Output
32
Tap B1 Bit 12
Tap B1 Bit 12
Digital Output
33
VSS
VSS
Ground
34
VDDA
VDDA
3.3V Analogue
35
VDD
VDD
3.3V supply
36
VDD
VDD
3.3V supply
37
VDD
VDD
3.3V supply
38
VDDA
VDDA
3.3V Analogue
39
N_Reset
N_Reset
Digital Input
40
VSS
Ground
Ground
41
Tap D1 Bit 12
Not connected
Digital Output
42
Tap D1 Bit 10
Not connected
Digital Output
43
Tap D1 Bit 8
Not connected
Digital Output
44
Tap D1 Bit 6
Not connected
Digital Output
45
VSS
VSS
Ground
46
Tap D1 Bit 4
Not connected
Digital Output
47
Tap D1 Bit 2
Not connected
Digital Output
48
Tap D1 Bit 0
Not connected
Digital Output
49
Tap D1 Bit 11
Not connected
Digital Output
50
Tap D1 Bit 9
Not connected
Digital Output
51
Tap D1 Bit 7
Not connected
Digital Output
52
Tap D1 Bit 5
Not connected
Digital Output
53
Tap D1 Bit 3
Not connected
Digital Output
54
Tap D1 Bit 1
Not connected
Digital Output
55
VSS
Ground
Ground
56
END_ADC_TAP C1/D1
Not connected
Digital Output
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DRAGSTER
Pin
Signal Name
DR-4k-3.5-LCC
DR-2x2k-7-LCC
Signal Name
DR-2k-7-LCC
Type
57
Pixel_CLK_Tap C1/D1
Not connected
Digital Output
58
Tap C1 Bit 0
Not connected
Digital Output
59
Tap C1 Bit 2
Not connected
Digital Output
60
Tap C1 Bit 4
Not connected
Digital Output
61
Tap C1 Bit 6
Not connected
Digital Output
62
Tap C1 Bit 8
Not connected
Digital Output
63
Tap C1 Bit 10
Not connected
Digital Output
64
Tap C1 Bit 12
Not connected
Digital Output
65
LVAL Tap C1/D1
Not connected
Digital Output
66
VSS
Ground
Ground
67
MISO C1/D1
Not connected
Digital Output
68
Tap C1 Bit 1
Not connected
Digital Output
69
Tap C1 Bit 3
Not connected
Digital Output
70
Tap C1 Bit 5
Not connected
Digital Output
71
Tap C1 Bit 7
Not connected
Digital Output
72
Tap C1 Bit 9
Not connected
Digital Output
73
VSS
Ground
Ground
74
Tap C1 Bit 11
Not connected
Digital Output
75
RESET_CDS
Digital Input
Digital Input
76
N_CS C1/D1
Not connected
Digital Input
77
MOSI
Digital Input
Digital Input
78
Main_CLK
Digital Input
Digital Input
79
Load_Pulse
Digital Input
Digital Input
80
VSS
Ground
Ground
81
VDD
3.3V
3.3V
82
VDD
3.3V
3.3V
83
VDDA
VDDA
3.3V Analogue
84
VDDA
VDDA
3.3V Analogue
85
N_CS A1/B1
Digital Input
Digital Input
86
SAMPLE
Digital Input
Digital Input
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DRAGSTER
Pin
Signal Name
DR-4k-3.5-LCC
DR-2x2k-7-LCC
Signal Name
DR-2k-7-LCC
Type
87
RST_CVC
Digital Input
Digital Input
88
SCLK
Digital Input
Digital Input
89
MISO A1/B1
Digital Output
Digital Output
90
VSS
Ground
Ground
From LCC version v2.0 there is a separation from chip analogue power to other supplies but
without separation on GND pins.
12.2 Connectors for different versions of Invar headboard packages
All Dragster modules, have up to 4 Molex connectors with 120 pin and reference 0553391208.
The below table indicates which connectors are present for the different chip versions.
Chip version
Present connectors
Connector Reference
Not applied
-----------------------
Connector 1
Molex 055339-1208
Connector 1 & Connector 2
Molex 055339-1208
Connector 1& Connector 3
Molex 055339-1208
Connector 1 - 4
Molex 055339-1208
DR-2k-7-LCC
DR-2x2k-7-LCC
DR-4k-3.5-LCC
DR-4k-7-Invar
DR-2k-7-Invar
DR-2x2k-7-Invar
DR-4k-3.5-Invar
DR-2x4k-7-Invar
DR-6k-7-Invar
DR-8k-3.5-Invar
DR-8k-7-Invar
DR-2x8k-7-Invar
DR-16k-3.5-Invar
Table 14: Connectors for different chip versions
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DRAGSTER
12.2.1 Connector number identification and pin numbers
60
1
60
Connector 4
1
Connector 2
120
61
120
61
60
1
60
1
Connector 3
120
Connector 1
61
120
61
Fig 42: Identification of connector number and pin numbers, DR-16K-3.5 back view
Date:
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DRAGSTER
12.3 Connector signal assignment for Invar head board DR-2x2k-7-Invar,
DR-4k-3.5-Invar, DR-2k-7-Invar
For DR-2k-7-Invar Connector 2 is present but not required. Only the powers present on the
connector are routed to the sensor. Connector 2 can be left completely unconnected for DR2k-7-Invar.
12.3.1 Connector 1
Date:
Pin Number
Signal Name
Signal Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N_CS_AB_1
MISO_AB_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_AB_1
VDDIO
END_ADC_AB_1
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
VDDIO
TEST_MUX_AB_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
VSSESD/IO
PIXEL_CLK_AB_1
VCLAMP_AB_1
SAMPLE_AB
RST_CDS_AB
RST_CVC_AB
Not Connected
SCLK_AB_EF
MOSI_AB_EF
Not Connected
VDDA
VDD_BULK
Dig in
Dig out
VDDA
VDDD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDDD
GND
GND
GND
GND
Dig_out
VDDA
Dig in
Dig in
Dig in
06/06/17
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Dig in
dig in
VDDA
VDD_Bulk
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DRAGSTER
Pin Number
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Date:
06/06/17
Signal Name
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
Not Connected
VDDIO
Not Connected
VDDA
VDDD
VSSA
VSSD
VDDIO
Not Connected
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
N_RESET_AB
Not Connected
Not Connected
VSSESD/IO
LVAL_AB_1
BIT_12_TAP_A1
BIT_11_TAP_A1
BIT_10_TAP_A1
BIT_09_TAP_A1
BIT_08_TAP_A1
BIT_07_TAP_A1
BIT_06_TAP_A1
BIT_05_TAP_A1
BIT_04_TAP_A1
BIT_03_TAP_A1
BIT_02_TAP_A1
BIT_01_TAP_A1
BIT_00_TAP_A1
VSSESD/IO
BIT_00_TAP_B1
BIT_01_TAP_B1
BIT_02_TAP_B1
BIT_03_TAP_B1
BIT_04_TAP_B1
BIT_05_TAP_B1
BIT_06_TAP_B1
BIT_07_TAP_B1
Version 3.2.8
Signal Type
VDDD
VDDESD
GND
GND
GND
VDDIO
VDDA
VDDD
GND
GND
VDDIO
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Page:
81/101
DRAGSTER
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
BIT_08_TAP_B1
BIT_09_TAP_B1
BIT_10_TAP_B1
BIT_11_TAP_B1
BIT_12_TAP_B1
MAIN_CLK
VSSESD/IO
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
VSSESD/IO
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
VSSESD/IO
Dig out
Dig out
Dig out
Dig out
Dig out
Dig in
GND
GND
GND
Note: SCLK and MOSI are connected between connector 1 and connector 3
in the headboard, resulting names are SCLK_AB_EF and MOSI_AB_EF.
User just needs to provide the headboard one pair of this signals to
connector 1 or 3 to communicate with the SPI's, taking the advantage that 2
IO lines from the control unit (FPGA or CPLD) are saved. Each SPI can be
selected individually by selecting respective negative chip select pin.
Date:
06/06/17
Version 3.2.8
Page:
82/101
DRAGSTER
12.3.2 Connector 2
Date:
Pin Number
Signal Name
Signal Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
VSSESD/IO
LVAL_CD_1
BIT_12_TAP_C1
BIT_11_TAP_C1
BIT_10_TAP_C1
BIT_09_TAP_C1
BIT_08_TAP_C1
BIT_07_TAP_C1
BIT_06_TAP_C1
BIT_05_TAP_C1
BIT_04_TAP_C1
BIT_03_TAP_C1
BIT_02_TAP_C1
BIT_01_TAP_C1
BIT_00_TAP_C1
VSSESD/IO
BIT_00_TAP_D1
BIT_01_TAP_D1
BIT_02_TAP_D1
BIT_03_TAP_D1
BIT_04_TAP_D1
BIT_05_TAP_D1
BIT_06_TAP_D1
BIT_07_TAP_D1
BIT_08_TAP_D1
BIT_09_TAP_D1
BIT_10_TAP_D1
BIT_11_TAP_D1
BIT_12_TAP_D1
Not Connected
VSSESD/IO
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
VSSESD/IO
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
06/06/17
Version 3.2.8
GND
GND
Page:
83/101
DRAGSTER
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Date:
06/06/17
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
VSSESD/IO
N_CS_CD_1
MISO_CD_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_CD_1
VDDIO
END_ADC_CD_1
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
VDDIO
TEST_MUX_CD_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
VSSESD/IO
PIXEL_CLK_CD_1
VCLAMP_CD_1
SAMPLE_CD
RST_CDS_CD
RST_CVC_CD
Not Connected
SCLK_CD_GH
MOSI_CD_GH
Not Connected
VDDA
VDD_BULK
Version 3.2.8
GND
Dig in
Dig out
VDDA
VDDD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDDD
GND
GND
GND
GND
Dig_out
VDDA
Dig in
Dig in
Dig in
Dig in
Dig in
VDDA
VDD_Bulk
Page:
84/101
DRAGSTER
Pin Number
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Signal Name
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
Not Connected
VDDIO
Not Connected
VDDA
VDDD
VSSA
VSSD
VDDIO
Not Connected
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
N_RESET_CD
Not Connected
Not Connected
Signal Type
VDDD
VDDESD
GND
GND
GND
VDDIO
VDDA
VDDD
GND
GND
VDDIO
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
Note: SCLK and MOSI are connected between connector 2 and connector 4
in the headboard, resulting names are SCLK_CD_GH and MOSI_CD_GH.
The user just need to provide to the headboard one pair of this signals to
connector 2 or 4 to communicate with the SPI's, taking the advantage that 2
IO lines from the control unit (FPGA or CPLD) are saved. Each SPI can be
selected individually by selecting respective negative chip select pin.
Date:
06/06/17
Version 3.2.8
Page:
85/101
DRAGSTER
12.4 Connector signal assignment for Invar head board variations DR-4k7, DR-8k-7, DR-8k-3.5, DR-16k-3.5, DR-2x4k-7, DR-2x8k-7
The signal assignment for all Invar type headboards is identical, though for smaller chip
versions some connectors may not be present. The pin numbers are cyclic, when looking on
the connector form the connector side right to left.
12.4.1 Connector 1
Date:
Pin Number
Signal Name
Signal Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
N_CS_AB_1
MISO_AB_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_AB_1
VDDIO
END_ADC_AB_1
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
VDDIO
TEST_MUX_AB_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
VSSESD/IO
PIXEL_CLK_AB_1
VCLAMP_AB_1
SAMPLE_AB
RST_CDS_AB
RST_CVC_AB
N_CS_AB_2
SCLK_AB_EF
MOSI_AB_EF
MISO_AB_2
VDDA
VDD_BULK
VDDD
VDDESD
Dig in
Dig out
VDDA
VDDD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDDD
GND
GND
GND
GND
Dig_out
VDDA
Dig in
Dig in
Dig in
Dig in
Dig in
dig in
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
06/06/17
Version 3.2.8
Page:
86/101
DRAGSTER
Date:
Pin Number
Signal Name
Signal Type
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
VSSA
VSS_BULK
VSSD
LOAD_PULSE_AB_2
VDDIO
END_ADC_AB_2
VDDA
VDDD
VSSA
VSSD
VDDIO
TEST_MUX_AB_2
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
N_RESET_AB
PIXEL_CLOCK_AB_2
VCLAMP_AB_2
VSSESD/IO
LVAL_AB_1
BIT_12_TAP_A1
BIT_11_TAP_A1
BIT_10_TAP_A1
BIT_09_TAP_A1
BIT_08_TAP_A1
BIT_07_TAP_A1
BIT_06_TAP_A1
BIT_05_TAP_A1
BIT_04_TAP_A1
BIT_03_TAP_A1
BIT_02_TAP_A1
BIT_01_TAP_A1
BIT_00_TAP_A1
VSSESD/IO
BIT_00_TAP_B1
BIT_01_TAP_B1
BIT_02_TAP_B1
BIT_03_TAP_B1
BIT_04_TAP_B1
BIT_05_TAP_B1
BIT_06_TAP_B1
BIT_07_TAP_B1
BIT_08_TAP_B1
BIT_09_TAP_B1
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDDD
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
Dig out
VDDA
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
06/06/17
Version 3.2.8
Page:
87/101
DRAGSTER
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
BIT_10_TAP_B1
BIT_11_TAP_B1
BIT_12_TAP_B1
MAIN_CLK
VSSESD/IO
LVAL_AB_2
BIT_12_TAP_A2
BIT_11_TAP_A2
BIT_10_TAP_A2
BIT_09_TAP_A2
BIT_08_TAP_A2
BIT_07_TAP_A2
BIT_06_TAP_A2
BIT_05_TAP_A2
BIT_04_TAP_A2
BIT_03_TAP_A2
BIT_02_TAP_A2
BIT_01_TAP_A2
BIT_00_TAP_A2
VSSESD/IO
BIT_00_TAP_B2
BIT_01_TAP_B2
BIT_02_TAP_B2
BIT_03_TAP_B2
BIT_04_TAP_B2
BIT_05_TAP_B2
BIT_06_TAP_B2
BIT_07_TAP_B2
BIT_08_TAP_B2
BIT_09_TAP_B2
BIT_10_TAP_B2
BIT_11_TAP_B2
BIT_12_TAP_B2
VSSESD/IO
Dig out
Dig out
Dig out
Dig in
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Note: SCLK and MOSI are connected between connector 1 and connector 3
in the headboard, resulting names are SCLK_AB_EF and MOSI_AB_EF.
User just need to provide to the headboard one pair of this signals to
connector 1 or 3 to communicate with the SPI's, taking the advantage that 2
IO lines from the control unit (FPGA or CPLD) are saved. Each SPI can be
selected individually by selecting respective negative chip select pin.
Date:
06/06/17
Version 3.2.8
Page:
88/101
DRAGSTER
12.4.2 Connector 2
Date:
Pin Number
Signal Name
Signal Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
VSSESD/IO
LVAL_CD_1
BIT_12_TAP_C1
BIT_11_TAP_C1
BIT_10_TAP_C1
BIT_09_TAP_C1
BIT_08_TAP_C1
BIT_07_TAP_C1
BIT_06_TAP_C1
BIT_05_TAP_C1
BIT_04_TAP_C1
BIT_03_TAP_C1
BIT_02_TAP_C1
BIT_01_TAP_C1
BIT_00_TAP_C1
VSSESD/IO
BIT_00_TAP_D1
BIT_01_TAP_D1
BIT_02_TAP_D1
BIT_03_TAP_D1
BIT_04_TAP_D1
BIT_05_TAP_D1
BIT_06_TAP_D1
BIT_07_TAP_D1
BIT_08_TAP_D1
BIT_09_TAP_D1
BIT_10_TAP_D1
BIT_11_TAP_D1
BIT_12_TAP_D1
NC
VSSESD/IO
LVAL_CD_2
BIT_12_TAP_C2
BIT_11_TAP_C2
BIT_10_TAP_C2
BIT_09_TAP_C2
BIT_08_TAP_C2
BIT_07_TAP_C2
BIT_06_TAP_C2
BIT_05_TAP_C2
BIT_04_TAP_C2
BIT_03_TAP_C2
BIT_02_TAP_C2
BIT_01_TAP_C2
BIT_00_TAP_C2
VSSESD/IO
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
not connected
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
06/06/17
Version 3.2.8
Page:
89/101
DRAGSTER
Date:
Pin Number
Signal Name
Signal Type
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
BIT_00_TAP_D2
BIT_01_TAP_D2
BIT_02_TAP_D2
BIT_03_TAP_D2
BIT_04_TAP_D2
BIT_05_TAP_D2
BIT_06_TAP_D2
BIT_07_TAP_D2
BIT_08_TAP_D2
BIT_09_TAP_D2
BIT_10_TAP_D2
BIT_11_TAP_D2
BIT_12_TAP_D2
VSSESD/IO
N_CS_CD_1
MISO_CD_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_CD_1
VDDIO
END_ADC_CD_1
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
VDDIO
TEST_MUX_CD_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
VSSESD/IO
PIXEL_CLK_CD_1
VCLAMP_CD_1
SAMPLE_CD
RST_CDS_CD
RST_CVC_CD
N_CS_CD_2
SCLK_CD_GH
MOSI_CD_GH
MISO_CD_2
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig in
Dig out
VDDA
VDDD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDDD
GND
GND
GND
GND
Dig_out
VDDA
Dig in
Dig in
Dig in
Dig in
Dig in
Dig in
Dig out
06/06/17
Version 3.2.8
Page:
90/101
DRAGSTER
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_CD_2
VDDIO
END_ADC_CD_2
VDDA
VDDD
VSSA
VSSD
VDDIO
TEST_MUX_CD_2
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
N_RESET_CD
PIXEL_CLK_CD_2
VCLAMP_CD_2
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDDD
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
Dig_out
VDDA
Note: SCLK and MOSI are connected between connector 2 and connector 4
in the headboard, resulting names are SCLK_CD_GH and MOSI_CD_GH.
The user just need to provide to the headboard one pair of this signals to
connector 2 or 4 to communicate with the SPI's, taking the advantage that 2
IO lines from the control unit (FPGA or CPLD) are saved. Each SPI can be
selected individually by selecting respective negative chip select pin.
Date:
06/06/17
Version 3.2.8
Page:
91/101
DRAGSTER
12.4.3 Connector 3
Date:
Pin Number
Signal Name
Signal Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
N_CS_EF_1
MISO_EF_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_EF_1
VDDIO
END_ADC_EF_1
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
VDDIO
TEST_MUX_EF_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
VSSESD/IO
PIXEL_CLK_EF_1
VCLAMP_EF_1
SAMPLE_EF
RST_CDS_EF
RST_CVC_EF
N_CS_EF_2
SCLK_AB_EF
MOSI_AB_EF
MISO_EF_2
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_EF_2
VDDIO
END_ADC_EF_2
VDDA
VDDD
Dig in
Dig out
VDDA
VDDD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDDD
GND
GND
GND
GND
Dig_out
VDDA
Dig in
Dig in
Dig in
Dig in
Dig in
dig in
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDDD
06/06/17
Version 3.2.8
Page:
92/101
DRAGSTER
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Date:
06/06/17
VSSA
VSSD
VDDIO
TEST_MUX_EF_2
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
N_RESET_EF
PIXEL_CLOCK_EF_2
VCLAMP_EF_2
VSSESD/IO
LVAL_EF_1
BIT_12_TAP_E1
BIT_11_TAP_E1
BIT_10_TAP_E1
BIT_09_TAP_E1
BIT_08_TAP_E1
BIT_07_TAP_E1
BIT_06_TAP_E1
BIT_05_TAP_E1
BIT_04_TAP_E1
BIT_03_TAP_E1
BIT_02_TAP_E1
BIT_01_TAP_E1
BIT_00_TAP_E1
VSSESD/IO
BIT_00_TAP_F1
BIT_01_TAP_F1
BIT_02_TAP_F1
BIT_03_TAP_F1
BIT_04_TAP_F1
BIT_05_TAP_F1
BIT_06_TAP_F1
BIT_07_TAP_F1
BIT_08_TAP_F1
BIT_09_TAP_F1
BIT_10_TAP_F1
BIT_11_TAP_F1
BIT_12_TAP_F1
MAIN_CLK
VSSESD/IO
LVAL_EF_2
BIT_12_TAP_E2
BIT_11_TAP_E2
BIT_10_TAP_E2
BIT_09_TAP_E2
Version 3.2.8
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
Dig out
VDDA
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig in
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Page:
93/101
DRAGSTER
Date:
Pin Number
Signal Name
Signal Type
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
BIT_08_TAP_E2
BIT_07_TAP_E2
BIT_06_TAP_E2
BIT_05_TAP_E2
BIT_04_TAP_E2
BIT_03_TAP_E2
BIT_02_TAP_E2
BIT_01_TAP_E2
BIT_00_TAP_E2
VSSESD/IO
BIT_00_TAP_F2
BIT_01_TAP_F2
BIT_02_TAP_F2
BIT_03_TAP_F2
BIT_04_TAP_F2
BIT_05_TAP_F2
BIT_06_TAP_F2
BIT_07_TAP_F2
BIT_08_TAP_F2
BIT_09_TAP_F2
BIT_10_TAP_F2
BIT_11_TAP_F2
BIT_12_TAP_F2
VSSESD/IO
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
06/06/17
Version 3.2.8
Page:
94/101
DRAGSTER
12.4.4 Connector 4
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Date:
06/06/17
Signal Name
VSSESD/IO
LVAL_GH_1
BIT_12_TAP_G1
BIT_11_TAP_G1
BIT_10_TAP_G1
BIT_09_TAP_G1
BIT_08_TAP_G1
BIT_07_TAP_G1
BIT_06_TAP_G1
BIT_05_TAP_G1
BIT_04_TAP_G1
BIT_03_TAP_G1
BIT_02_TAP_G1
BIT_01_TAP_G1
BIT_00_TAP_G1
VSSESD/IO
BIT_00_TAP_H1
BIT_01_TAP_H1
BIT_02_TAP_H1
BIT_03_TAP_H1
BIT_04_TAP_H1
BIT_05_TAP_H1
BIT_06_TAP_H1
BIT_07_TAP_H1
BIT_08_TAP_H1
BIT_09_TAP_H1
BIT_10_TAP_H1
BIT_11_TAP_H1
BIT_12_TAP_H1
NC
VSSESD/IO
LVAL_GH_2
BIT_12_TAP_G2
BIT_11_TAP_G2
BIT_10_TAP_G2
BIT_09_TAP_G2
BIT_08_TAP_G2
BIT_07_TAP_G2
BIT_06_TAP_G2
BIT_05_TAP_G2
BIT_04_TAP_G2
BIT_03_TAP_G2
BIT_02_TAP_G2
BIT_01_TAP_G2
BIT_00_TAP_G2
VSSESD/IO
BIT_00_TAP_H2
Version 3.2.8
Signal Type
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
not connected
GND
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig out
Page:
95/101
DRAGSTER
Date:
Pin Number
Signal Name
Signal Type
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
BIT_01_TAP_H2
BIT_02_TAP_H2
BIT_03_TAP_H2
BIT_04_TAP_H2
BIT_05_TAP_H2
BIT_06_TAP_H2
BIT_07_TAP_H2
BIT_08_TAP_H2
BIT_09_TAP_H2
BIT_10_TAP_H2
BIT_11_TAP_H2
BIT_12_TAP_H2
VSSESD/IO
N_CS_GH_1
MISO_GH_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_GH_1
VDDIO
END_ADC_GH_1
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
VDDIO
TEST_MUX_GH_1
VDDA
VDDD
VSSA
VSS_BULK
VSSD
VSSESD/IO
PIXEL_CLK_GH_1
VCLAMP_GH_1
SAMPLE_GH
RST_CDS_GH
RST_CVC_GH
N_CS_GH_2
SCLK_CD_GH
MOSI_CD_GH
MISO_GH_2
VDDA
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
Dig out
GND
Dig in
Dig out
VDDA
VDDD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDDD
GND
GND
GND
GND
Dig_out
VDDA
Dig in
Dig in
Dig in
Dig in
Dig in
Dig in
Dig out
VDDA
06/06/17
Version 3.2.8
Page:
96/101
DRAGSTER
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Date:
06/06/17
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
LOAD_PULSE_GH_2
VDDIO
END_ADC_GH_2
VDDA
VDDD
VSSA
VSSD
VDDIO
TEST_MUX_GH_2
VDDA
VDD_BULK
VDDD
VDDESD
VSSA
VSS_BULK
VSSD
N_RESET_GH
PIXEL_CLK_GH_2
VCLAMP_GH_2
Version 3.2.8
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
VDDIO
Dig out
VDDA
VDDD
GND
GND
VDDIO
analogue monitor leave n.c.
VDDA
VDD_Bulk
VDDD
VDDESD
GND
GND
GND
Dig in
Dig_out
VDDA
Page:
97/101
DRAGSTER
12.5 Connector signal assignment for Invar head board DR-6K-7
Pin Number
Date:
Signal Name
Bottom, Connector 1
Top, Connector 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
N_CS_AB_1
MISO_AB_1
VDDA
VDDD
GND_D
GND_D
GND_A
Load_Pulse_AB_1
VDDIO
End_ADC_AB_1
VDDA
VDD_Bulk
VDDD
VDDESD
GND_D
GND_D
GND_A
VDDIO
Test_Mux
VDDA
VDDD
GND_D
GND_D
GND_D
GND_A
Pixel_Clk_AB_1
GND_D
LVAL_EF_1
06/06/17
Version 3.2.8
Not connected
Sample_AB
RST_CDS_AB
RST_CVC_AB
N_CS_AB_2
SCLK_AB_EF
MOSI_AB_EF
MISO_AB_2
VDDA
VDD_BULK
VDDD
VDDESD
GND_D
GND_D
GND_A
Load_Pulse_AB_2
Not connected
BIT_11_TAP_A1
BIT_10_TAP_A1
BIT_09_TAP_A1
BIT_08_TAP_A1
BIT_07_TAP_A1
BIT_06_TAP_A1
BIT_05_TAP_A1
BIT_04_TAP_A1
BIT_03_TAP_A1
BIT_02_TAP_A1
BIT_01_TAP_A1
BIT_00_TAP_A1
GND_D
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
GND_D
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Page:
98/101
DRAGSTER
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Date:
06/06/17
VDDIO
End_ADC_AB_2
VDDA
VDDD
GND_D
GND_A
VDDIO
Not connected
VDDA
VDD_Bulk
VDDD
VDDESD
GND_D
GND_D
GND_A
N_Reset_AB
Pixel_Clk_AB_2
Not connected
GND_D
LVAL_AB_1
Not connected
BIT_00_TAP_B1
BIT_01_TAP_B1
BIT_02_TAP_B1
BIT_03_TAP_B1
BIT_04_TAP_B1
BIT_05_TAP_B1
BIT_06_TAP_B1
BIT_07_TAP_B1
BIT_08_TAP_B1
BIT_09_TAP_B1
BIT_10_TAP_B1
BIT_11_TAP_B1
GND_D
BIT_11_TAP_A2
BIT_10_TAP_A2
BIT_09_TAP_A2
BIT_08_TAP_A2
BIT_07_TAP_A2
BIT_06_TAP_A2
BIT_05_TAP_A2
BIT_04_TAP_A2
BIT_03_TAP_A2
BIT_02_TAP_A2
BIT_01_TAP_A2
BIT_00_TAP_A2
Not connected
Main_Clk
GND_D
Version 3.2.8
Not connected
Not connected
Not connected
GND_D
BIT_00_TAP_F1
BIT_01_TAP_F1
BIT_02_TAP_F1
BIT_03_TAP_F1
BIT_04_TAP_F1
BIT_05_TAP_F1
BIT_06_TAP_F1
BIT_07_TAP_F1
BIT_08_TAP_F1
BIT_09_TAP_F1
BIT_10_TAP_F1
BIT_11_TAP_F1
Not connected
GND_D
N_CS_EF_1
MISO_EF_1
Not connected
Not connected
GND_D
GND_D
GND_A
Load_Pulse_EF_1
Not connected
End_ADC_EF_1
Not connected
Not connected
Not connected
Not connected
GND_D
GND_D
GND_A
Not connected
Not connected
Not connected
Not connected
GND_D
GND_D
GND_D
GND_A
Pixel_Clk_EF_1
Not connected
Sample_EF
RST_CDS_EF
RST_CVC_EF
ID_Chip
Page:
99/101
DRAGSTER
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Date:
06/06/17
LVAL_AB_2
Not connected
BIT_00_TAP_B2
BIT_01_TAP_B2
BIT_02_TAP_B2
BIT_03_TAP_B2
BIT_04_TAP_B2
BIT_05_TAP_B2
BIT_06_TAP_B2
BIT_07_TAP_B2
BIT_08_TAP_B2
BIT_09_TAP_B2
BIT_10_TAP_B2
BIT_11_TAP_B2
GND_D
BIT_11_TAP_E1
BIT_10_TAP_E1
BIT_09_TAP_E1
BIT_08_TAP_E1
BIT_07_TAP_E1
BIT_06_TAP_E1
BIT_05_TAP_E1
BIT_04_TAP_E1
BIT_03_TAP_E1
BIT_02_TAP_E1
BIT_01_TAP_E1
BIT_00_TAP_E1
Not connected
GND_D
Version 3.2.8
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
GND_D
GND_D
GND_A
Not connected
Not connected
Not connected
Not connected
3.3V_Digital
GND_D
GND_A
Not connected
Not connected
Not connected
Not connected
Not connected
3.3V_Digital
GND_D
GND_D
GND_A
N_Reset_EF
Not connected
Not connected
Page:
100/101
DRAGSTER
End of Document
Date:
06/06/17
Version 3.2.8
Page:
101/101
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